A method of preparing an integrated electronic component by forming a circuit pattern on a semiconductor wafer for example of silicon or gallium-arsenic, bonding the integrated electronic component to an adhesive sheet having a base film layer and an adhesive layer, fixing it additionally to a ring frame, cutting (dicing) it into separate semiconductor chips, expanding the film as needed, picking up the semiconductor chips, and fixing the semiconductor chips for example onto a lead frame with an adhesive is practiced widely in manufacture of electronic components such as ICs.
In such a manufacturing method, proposed were methods of using a multilayer adhesive sheet (die attach film-integrated sheet) having both a function of the adhesive sheet for dicing and a function of the adhesive for fixing the chips for example to lead frame, which is prepared by integrating the die attach film with the adhesive sheet by lamination (see Patent Documents 1 and 2). Use of the die attach film-integrated sheet in manufacture of electronic components gives an advantage that it is possible to eliminate the adhesive-coating step and control the thickness of the adhesive region and suppress exudation thereof, compared to the method of using an adhesive.